This invention relates to semiconductor devices, and more particularly to circuits for rapid testing of registers and the like in dynamic memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. When memory devices of this type are manufactured in higher densities, such as 256K and 1-Megabit and beyond, the problem of testing all of the cells and all of the other circuits on the chip becomes formidible.
Testing problems are increased when functions are added to the memory devices. For example, a self-refresh function as disclosed in U.S. Pat. No. 4,207,618, issued to White and Rao, assigned to Texas Instruments, requires a row address counter to be included on the chip. In a 1-Meg device, refreshed at 512 cycles per period, this means that a 9-bit counter is required; a 9-bit counter needs 512 cycles to be completely tested by conventional methods. Similarly, a counter used in a device having an extended nibble mode may require a lengthy test period.
It is the principal object of this invention to provide improved test circuitry for high density dynamic RAM devices, particularly for testing counter registers and the like. Another object is to provide testing circuitry for a CMOS dynamic RAM in which the testing time is minimized, and the circuitry added to the device is minimized. A further object is to provide high speed test circuitry for semiconductor devices which contain registers for counting and the like.